1. Field of the Invention
The invention relates to phase-locked loop circuits (PLLs), and more specifically to a phase-locked loop with compensated loop latency.
2. Description of the Related Art
With increased clock rates, low-skew clock distributions are becoming increasingly critical to achieving design speed objectives. High-speed circuits may also require clocks with programmable duty cycle and delay. For all these applications, a comprehensive clock management may be employed on a chip. The phase-locked loop circuits (PLLs) are widely used to achieve low clock skew distributions and stringent frequency requirements.
FIG. 1 is a schematic diagram of a conventional PLL 100. The PLL 100 comprises an analog-to-digital converter (ADC) 102, a phase detector 104, a loop filter 106 and a voltage-controlled oscillator (VCO) 108. The ADC 102 receives an analog input signal and an output clock clkout functioning as a clock for the ADC 102 to generate a digital signal to the phase detector 104. The phase detector 104 generates an estimated phase error phase_err according to the received digital signal from the ADC 102. The loop filter 106, such as a proportional integral (PI) filter, operates as an integrator to generate a filtered signal to the VCO 108 according to the estimated phase error phase_err received from the phase detector 104. The VCO 108 then generates the output clock clkout adjusted by the filtered signal. In addition to acting as the output signal of PLL 100, the output clock clkout is fed back to the ADC 102 as stated, forming the closed-loop PLL circuit.
However, loop latency may be introduced in the PLL circuits, causing instability and degrading performance thereof. Thus, it is advantageous to compensate the effects caused by the loop latency in PLLs, obtaining a loop latency compensated PLL.